IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

1

Diagnosing arbitrary defects in logic designs using single location at a time (SLAT)

Huisman, L.M.

Journal:

Année:

2004

Langue:

english

Fichier:

PDF, 335 KB

english, 2004

2

Optimization-intensive watermarking techniques for decision problems

Wong, J.L., Gang Qu, Potkonjak, M.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 321 KB

english, 2004

3

Fast postplacement optimization using functional symmetries

Chih-Wei Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Marek-Sadowska, M., Chung-Kuan Cheng, Sao-Jie Chen

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 757 KB

english, 2004

4

IEEE Circuits and Systems Society Information

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 34 KB

english, 2004

5

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Call for Papers

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Fichier:

PDF, 164 KB

2004

6

Nontree routing for reliability and yield improvement [IC layout]

Kahng, A.B., Bao Liu, Mandoiu, I.I.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 494 KB

english, 2004

7

COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems

Dick, R.P., Jha, N.K.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 364 KB

english, 2004

8

Constrained test generation for embedded synchronous sequential circuits with serial-input access

Pomeranz, I.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 409 KB

english, 2004

9

A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]

Li-Da Huang, Xiaoping Tang, Hua Xiang, Wong, D.F., I-Min Liu

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 833 KB

english, 2004

10

A library compatible driver output model for on-chip RLC transmission lines

Agarwal, K., Sylvester, D., Blaauw, D.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 563 KB

english, 2004

11

Coupling-aware high-level interconnect synthesis [IC layout]

Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 577 KB

english, 2004

12

Common-case computation: a high-level energy and performance optimization technique

Lakshminarayana, G., Raghunathan, A., Khouri, K.S., Jha, N.K., Dey, S.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 345 KB

english, 2004

13

Optimizing designs using the addition of deflection operations

Wong, J.L., Potkonjak, M., Dey, S.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 400 KB

english, 2004

14

Physically rigorous modeling of internal laser-probing techniques for microstructured semiconductor devices

Thalhammer, R.K., Wachutka, G.K.M.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 859 KB

english, 2004

15

Nonrectangular shaping and sizing of soft modules for floorplan-design improvement

Chu, C.C.N., Young, E.F.Y.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 687 KB

english, 2004

16

System modeling and transformational design refinement in ForSyDe [formal system design]

Sander, I., Jantsch, A.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 412 KB

english, 2004

17

Hierarchical current-density verification in arbitrarily shaped metallization patterns of analog circuits

Jerke, G., Lienig, J.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 1.02 MB

english, 2004

18

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique

Alpert, C., Chu, C., Gandham, G., Hrkic, M., Jiang Hu, Kashyap, C., Quay, S.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 270 KB

english, 2004

19

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Society Information

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 37 KB

english, 2004

21

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Langue:

english

Fichier:

PDF, 24 KB

english, 2004

22

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Society Information

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Fichier:

PDF, 527 KB

2004

23

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Copyright Form

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2004

Fichier:

PDF, 1.03 MB

2004

Volume 23; Issue 1

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Diagnosing arbitrary defects in logic designs using single location at a time (SLAT)

Optimization-intensive watermarking techniques for decision problems

Fast postplacement optimization using functional symmetries

IEEE Circuits and Systems Society Information

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Call for Papers

Nontree routing for reliability and yield improvement [IC layout]

COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems

Constrained test generation for embedded synchronous sequential circuits with serial-input access

A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]

A library compatible driver output model for on-chip RLC transmission lines

Coupling-aware high-level interconnect synthesis [IC layout]

Common-case computation: a high-level energy and performance optimization technique

Optimizing designs using the addition of deflection operations

Physically rigorous modeling of internal laser-probing techniques for microstructured semiconductor devices

Nonrectangular shaping and sizing of soft modules for floorplan-design improvement

System modeling and transformational design refinement in ForSyDe [formal system design]

Hierarchical current-density verification in arbitrarily shaped metallization patterns of analog circuits

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique

Table of contents

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Society Information

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Society Information

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Copyright Form