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Logic area reduction using the deep trench isolation technique based on 40 nm embedded PCM process
Du, Yuan, Ye, Yong, Jing, Weiliang, Li, Xiaoyun, Song, Zhitang, Chen, BomyVolume:
14
Année:
2017
Journal:
IEICE Electronics Express
DOI:
10.1587/elex.14.20170628
Fichier:
PDF, 1.92 MB
2017