[IEEE 2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) - Prague, Czech Republic (2018.7.2-2018.7.5)] 2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) - System-Level Behavioral Model of a 12-Bit 1.5-Bit Per Stage Pipelined ADC Based on Verilog ® =-AMS
Ponce-Hinestroza, Vicente Y., Gonzalez-Diaz, Victor R.Année:
2018
Langue:
english
DOI:
10.1109/SMACD.2018.8434881
Fichier:
PDF, 172 KB
english, 2018