
SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, USA (Sunday 23 February 2014)] Design-Process-Technology Co-optimization for Manufacturability VIII - Analysis and optimization of process-induced electromigration on signal interconnects in 16nm FinFET SoC (system-on-chip)
Sturtevant, John L., Capodieci, Luigi, Ban, Yongchan, Choi, Changseok, Shin, Hosoon, Kang, Yongseok, Paik, Woo HyunVolume:
9053
Année:
2014
Langue:
english
DOI:
10.1117/12.2046207
Fichier:
PDF, 766 KB
english, 2014