SPIE Proceedings [SPIE Microelectronic Manufacturing - Santa Clara, CA (Sunday 20 September 1998)] Microelectronic Device Technology II - Optimum junction depth design of the S/D extension regions (MDD) for sub-0.18-μm CMOS technologies
Chao, Chih-Ping, Mehrotra, Manoj, Chen, Ih-Chin, Burnett, David, Wristers, Dirk, Tsuchiya, ToshiakiVolume:
3506
Année:
1998
Langue:
english
DOI:
10.1117/12.323982
Fichier:
PDF, 356 KB
english, 1998