
[IEEE 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) - Wien, Vienna, Austria (2016.1.25-2016.1.27)] 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) - A method for combined characterization of MOSFET threshold voltage and junction capacitance eliminating channel current effect
Tomaszewski, Daniel, Gluszko, Grzegorz, Malesinska, JolantaAnnée:
2016
Langue:
english
DOI:
10.1109/ULIS.2016.7440083
Fichier:
PDF, 1.89 MB
english, 2016