10–315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation
Song, Minyoung, Kwak, Young-Ho, Ahn, Sunghoon, Park, Hojin, Kim, ChulwooVolume:
21
Langue:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/tvlsi.2012.2227068
Date:
November, 2013
Fichier:
PDF, 2.20 MB
english, 2013