[IEEE ESSCIRC 2012 - 38th European Solid State Circuits Conference - Bordeaux, France (2012.09.17-2012.09.21)] 2012 Proceedings of the ESSCIRC (ESSCIRC) - A digital fractional-N PLL with a 3mW 0.004mm2 6-bit PVT and mismatch insensitive TDC
Kim, Hyung Seok, Ornelas, Carlos, Chandrashekar, Kailash, Su, Pin-en, Madoglio, Paolo, Li, Y. William, Ravi, AshokeAnnée:
2012
Langue:
english
DOI:
10.1109/ESSCIRC.2012.6341291
Fichier:
PDF, 774 KB
english, 2012